The heterogeneous multi-core platform provides flexibility for system design by integrating different types of processing cores, so that applications can dynamically select different types of processing cores according to their requirements and realize efficient operation of applications. With the development of semiconductor technology, the number of integrated cores on a single chip has increased, making the modern multi-core processors have a higher power density, and this will cause the chip temperature to rise, which will eventually cause a certain negative impact on the system performance. To make the performance advantages of heterogeneous multi-core processing system fully utilized, a dynamic mapping method was proposed to maximize the performance of heterogeneous multi-core systems under the premise of satisfying temperature safe power. In this method, two heterogeneous indices of heterogeneous multi-core systems including core type and thermal susceptibility were considered to determine the mapping scheme:the first heterogeneous index is the core type. Different types of processing cores have different characteristics, so they are suitable for processing different applications. The second heterogeneous index is thermal susceptibility. Different processing core positions on the chip have different thermal susceptibility. The processing cores closer to the center receive more heat transfer from other processing cores, so that they have higher temperature. For the above, a neural network performance predictor was created to match threads to processing core types, and the Thermal Safe Power (TSP) model was used to map the matched threads to specific locations on the chip. Experimental results show that the proposed method achieves about 53% increase of the average number of instructions executed by the program in each clock cycle-Instruction Per Cycle (IPC) under the premise of ensuring thermal safety constraints compared with the common Round Robin Scheduler (RRS).

Nowadays, with the development of semiconductor technology and the requirement of the diversification of applications, heterogeneous multi-core processors have been widely used in high-performance embedded systems. How to manage and distribute the available resources (such as processing cores) during running in order to meet the requirements in performance and power consumption of the system and the applications that the system runs is a main challenge that the system focuses. However, although some mainstream resource management techniques have achieved good results in terms of performance and/or power consumption optimization, they lack the strict reliability guarantee for the resource management component. Therefore, a method based on Discrete Controller Synthesis (DCS) was proposed to automatically and reliably design the online resource management scheme for heterogeneous multi-core systems, which applies DCS (which is formal and can construct management control components automatically) to the design of online resource management components for heterogeneous multi-core systems. In this method, the heterogeneous system’s running behaviors (such as how to distribute the processing cores to the applications) were described by using the formal models, and the online resource management problem was transformed to a DCS problem aiming at one system management objective (such as maximizing system performance). On this basis, the existing DCS tools were used to illustrate and validate the proposed method, and the scalability of the DCS method was evaluated.

Heterogeneous multi-core processor is the mainstream solution for modern embedded systems now. Good online mapping or scheduling approaches play important roles in improving their advantages of high performance and low power consumption. To deal with the problem of dynamic mapping and scheduling of applications on heterogeneous multi-core processing systems, a dynamic mapping and scheduling solution was proposed to effectively determine remapping time in order to maximize the system performance by using the machine learning based detection technology of quickly and accurately evaluating program performance and program behavior phase change. In this solution, by carefully selecting the static and dynamic features of processing cores and programs to running to effectively detect the difference in computing power and workload running behaviors brought by heterogeneous processing, a more accurate prediction model was built. At the same time, by introducing phase detection technology, the number of online mapping computations was reduced as much as possible, so as to provide more efficient scheduling scheme. Finally, the effectiveness of the proposed scheduling scheme was verified on the SPLASH-2 dataset. Experimental results showed that, compared to the Completely Fair Scheduler (CFS) of Linux, the proposed method achieved about 52% computing performance gains and 9.4% improvement on CPU resource utilization rate. It shows that the proposed method has excellent performance in system computing performance and processor resource utilization, and can effectively improve the dynamic mapping and scheduling effect of applications of heterogeneous multi-core systems.

Focusing on the increasing amount of test data in the development of Very Large Scale Integration (VLSI), a test data compression method based on tri-state signal was proposed. Firstly, the test set was optimized and pre-processed by performing partial input reduction and test vector reordering operations, improving the compatibility among test patterns while increasing the proportion of don't-care bit X in the test set. Then, the coding compression of tri-state signal was performed to the pre-processed test set, so that the test set was divided into multiple scan slices by using the characteristics of tri-state signal, and the tri-state signal was used to perform compatible coding compression on the scann slices. With various test rules considered, the test set compression ratio was improved. The experimental results show that, compared with the similar compression methods, the proposed method achieves a higher compression ratio, and the average test compression ratio reaches 76.17% without significant increase of test power and area overhead.

Traditional vision-based or sensor-based falling detection systems possess certain inherent shortcomings such as hardware dependence and coverage limitation, hence Fallsense, a passive falling detection method based on wireless Channel State Information (CSI) was proposed. The method was based on low-cost, pervasive and commercial WiFi devices. Firstly, the wireless CSI data was collected and preprocessed. Then a model of motion-signal analysis was built, where a lightweight dynamic template matching algorithm was designed to detect relevant fragments of real falling events from the time-series channel data in real time. Experiments in a large number of actual environments show that Fallsense can achieve high accuracy and low false positive rate, with an accuracy of 95% and a false positive rate of 2.44%. Compared with the classic WiFall system, Fallsense reduces the time complexity from O( mN log N) to O( N) ( N is the sample number, m is the feature number), and increases the accuracy by 2.69%, decreases the false positive rate by 4.66%. The experimental results confirm that this passive falling detection method is fast and efficient.

In order to solve the problem of high cost of chip testing in the process of Three-Dimensional (3D) chip manufacturing, a new scheduling method based on Time Division Multiplexing (TDM) was proposed to optimize the testing resources between layers, layer and core cooperatively. Firstly, the shift registers were arranged on each layer of 3D chip, and the testing frequency was divided properly between the layers and cores of the same layer under the control of shift register group on input data, so that the cores in different locations could be tested in parallel. Secondly, greedy algorithm was used to optimize the allocation of registers for reducing the free test cycles of core parallel test. Finally, Discrete Binary Particle Swarm Optimization (DBPSO) algorithm was used to find out the best 3D stack layout, so that the transmission potential of the Through Silicon Via (TSV) could be adequately used to improve the parallel testing efficiency and reduce the testing time. The experimental results show that, under the power constraints, the utilization rate of the optimized whole Test Access Mechanism (TAM) is increased by an average of 16.28%, and the testing time of the optimized 3D stack is reduced by an average of 13.98%. The proposed method can decrease the time and reduce the cost of testing.